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3.1.5.2 Offset Cancellation Phase Control Bits (OCPHASE[1:0])
The offset cancellation phase control bits control the offset cancellation start up phase. These bits can be written at any time
ENDINIT is ‘0’ if the OFFCFG_EN bit is set.
OFFCFG_EN
0
1
1
1
1
OCPHASE[1]
Don’t Care
0
0
1
1
OCPHASE[0]
Don’t Care
0
1
0
1
Writes to
OCPHASE[1:0]
Ignored
Accepted
Accepted
Accepted
Accepted
Offset Cancellation Phase
Continues from the previously written phase (OCPHASE[1:0]) as
specified in Section 3.8.4 .
Remains in Start 1 until OFFCFG_EN is cleared or ENDINIT is set
Remains in Start 2 until OFFCFG_EN is cleared or ENDINIT is set
Remains in Start 3 until OFFCFG_EN is cleared or ENDINIT is set
Remains in Normal Mode until OFFCFG_EN is cleared or ENDINIT is set
When ENDINIT is set, the OCPHASE[1:0] bits in a write command are ignored and the offset cancellation phase is set to “Nor-
mal”. This can only be changed by a device reset. The response to a register read or write of the DEVCTL register once ENDINIT
is set will return the last successfully written values of OCPHASE[1:0].
3.1.5.3 Offset Cancellation Configuration Enable Bit (OFFCFG_EN)
The offset cancellation phase configuration enable bit enables modification of the offset cancellation phase control bits
(OCPHASE[1:0]) as shown in Section 3.1.5.2
When ENDINIT is set, the OFFCFG_EN bit in a write command is ignored, and the offset cancellation phase is set to “Normal”.
This can only be changed by a device reset. The response to a register read or write of the DEVCTL register once ENDINIT is
set will return the last successfully written value of OFFCFG_EN.
3.1.5.4 Reserved Bits (DEVCTL[2:0])
Bits 2 through 0 of the DEVCTL register are reserved. A write to the reserved bits must always be logic ‘0’ for normal device
operation and performance.
3.1.6
Device Configuration Register (DEVCFG)
The device configuration register is a read/write register which contains data for general device configuration. The register can
be written during initialization but is locked once the ENDINIT bit is set. This register is included in the writable register CRC
check. Refer to Section 3.2.2 for details.
Table 8. Device Configuration Register
Location
Bit
Address
$0B
Register
DEVCFG
7
OC
6
Reserved
5
ENDINIT
4
SD
3
OFMON
2
A_CFG[2]
1
A_CFG[1]
0
A_CFG[0]
Reset Value
0
0
0
0
0
0
0
0
3.1.6.1 Offset Cancelled Data Selection Bits (OC)
The Offset Cancelled Data Selection Bit determines whether the SPI transmitted data is raw data or offset cancelled data.
OC
0
1
SPI Data
Offset Cancelled
Raw Data
If the OC bit is cleared (Offset Cancelled Data), then the Offset Monitor is automatically enabled (OFMON = ‘1’) regardless of
the value written to DEVCFG[3].
3.1.6.2 Reserved Bit (Reserved)
Bits 6 of the DEVCFG register is reserved. A write to the reserved bit must always be logic ‘0’ for normal device operation and
performance.
MMA655x
Sensor
14
Freescale Semiconductor, Inc.
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